Semiconductor memory cells are well known and have been used extensively for many years to store a binary bit of data as a "1" or a "0". Digital circuits and logic families have also been extensively used to perform functions on bits of binary data. Unfortunately, the data bit stored in the cell or processed within the digital circuit can be corrupted if the cell or circuit is exposed to an ionized particle such as an alpha particle, T, Ma, and P. Dressendorfer, Ionizing Radiation Effects in CMOS Devices & Circuits, New York, N.Y., John Wiley & Sons, 1989, Chapter 9. It is known that single event upsets (SEU) can occur due to a charged particle striking the cell or circuit. Further, in outer space, cosmic ions are abundant and are the principle source of SEUs in memory cells and circuits. The heavier ions have higher linear energy transfer compared to lighter ions. Accordingly, the stored data bit is more likely to be corrupted in an environment bombarded with heavy ionized particles.
The hardware in which the data is stored in memory cells and processed within digital circuits on satellites and spacecraft travelling in outer space needs to meet two important criteria. First, safeguarding the integrity of the stored and calculated data is critical because often data collected while in space is not easily duplicated, and the accuracy of the calculated data on a satellite or spacecraft is crucial to a space mission's success. Therefore, the hardware used to store and calculate the data must be SEU immune. Second, SEU immune hardware solution utilized in satellites and spacecraft are severely restricted in size and weight. Therefore, traditional SEU immune hardware solutions which contain only SEU immune components are too heavy and large to be suitable for travel in outer space.
A variety of techniques have been utilized to prevent the corruption of data stored in a memory cell and processed in a digital circuit when the cell or circuit is struck by a charged particle. For example, U.S. Pat. No. 5,111,429, issued May 5, 1992, to Sterling R. Whitaker entitled SINGLE EVENT UPSET HARDENING CMOS MEMORY CIRCUIT, discloses the design of single event upset (SEU) immune static RAM cells. In addition, U.S. Pat. No. 5,418,473, issued May 23, 1995, to John Canaris entitled SINGLE EVENT UPSET IMMUNE LOGIC FAMILY, discloses a complete logic family which is single event upset immune. The SEU immune RAM cells and logic family, described in U.S. Pat. Nos. 5,111,429 and 5,418,473, require substantial, additional hardware to achieve SEU immunity compared to equivalent non-SEU immune circuits. These patents are incorporate by reference. Unfortunately, the techniques utilized in the prior art to ensure that memory cells and circuits are SEU immune require substantial additional hardware.
For example, FIG. 1 illustrates the complexity of a transistor level logic diagram of an SEU immune inverter as described in U.S. Pat. No. 5,418,473. The inverter includes two transistor networks, a p-channel network and an n-channel network. The p-channel network is comprises transistors M1 and M2 and the n-channel network is comprised of transistors M3 and M4. A p-channel input PIN is coupled to the gate 10 of the transistor M1 to control the transistor M1. A drain 11 of the transistor is coupled to the power supply VDD. A drain 14 of the transistor M2 is coupled to a source 12 of the transistor M1 and also to an output POUT. A source 15 of the transistor M2 is coupled to the ground VSS.
An n-channel input NIN is coupled to a gate 19 of the transistor M4 to control the transistor M4. A source 21 of the transistor M4 is coupled to the ground VSS. A source 18 of the transistor M3 is coupled to a drain 20 of the transistor M4, a gate 13 of the transistor M2 and an output NOUT. A gate 16 of the transistor M3 is coupled to the source 12 of the transistor M1, the drain 14 of the transistor M2 and the output POUT. A drain 17 of the transistor M3 is coupled to the power supply VDD.
The p-channel and n-channel networks are cross coupled. In particular, the n-channel output NOUT is coupled to control the gate 13 of the p-channel load transistor M2. Also, the p-channel output POUT is coupled to control the gate 16 of the n-channel load transistor M3. The load transistors M2 and M3 are sized to be weak in comparison to the logic transistors M1 and M4.
All devices used in the SEU immune inverter are enhancement mode transistors. The logic family according to SEU immune inverter will operate with any type of transistor including enhancement, depletion or native MOS. The inverter is a two input/two output logic device with the input PIN driving only p-channel devices and the input NIN driving only n-channel devices. The output node POUT can provide a source of logic "1"'s which cannot be upset and the output node NOUT provides a source of logic "0"'s which cannot be upset. The transistor M2 is sized to be weak compared to the transistor M1 and the transistor M3 is sized to be weak compared to the transistor M4.
When the inputs to the inverter are a logic "0", the outputs POUT and NOUT are at a logic "1". In this state, only the output NOUT can be corrupted by an upset. If the output NOUT is hit, driving the node to a logic "0", the transistor M2 will turn on but cannot overdrive the transistor M1. The output POUT will remain at a logic "1", the transistor M3 will remain on, pulling the output NOUT back up to a logic "1". Conversely, if the inputs PIN and NIN are a logic "1", the outputs POUT and NOUT will be at a logic "0" and only the output POUT can be upset. If the output POUT is hit, driving the node to a logic "1", the transistor M3 will turn on but because it is weak compared to the transistor M4, the output NOUT will remain pulled down to a logic "0".
Further, according to the prior art, U.S. Pat. No. 5,418,473, SEU immune logic gates are not limited to inverters. It is known in the art that SEU immune NAND gates, NOR gates, AndNor gates, and OrNand gates can be created using the same technique for creating the above-described SEU immune inverter. In general, an SEU immune logic gate, implemented with the above technique, requires 2n+2 transistors, n being the number of gate inputs. In comparison, classical CMOS design requires 2n transistors to implement a gate. A complex circuit that is created from many logic gates which needs to be SEU immune will require many more transistors and traces. For a circuit to be completely SEU immune, each logic gate used within the circuit will require two additional transistors when compared to classical MOS design. The additional transistors will increase the power consumption, increase the number of traces, increase the package size and weight, and add to the complexity of the circuit.
What is needed is a circuit which has the properties of being SEU immune without suffering the drawbacks of extra weight and size due to additional hardware found in prior art SEU immune circuits.